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| Intel's 440BX
AGPset in Depth |
| The 440BX AGPset is the third generation Pentium II class
chipset from Intel. (The first and second generation being the 440FX PCIset and 440LX
AGPset, respectively.) Along with support for SDRAM (up to 1GB), AGP 2x at 133MHz, and
UltraDMA/33, the 440BX is the first chipset to support 100MHz memory bus speed. Pentium II
CPUs from 350MHz to 400MHz (currently) will be able to run at 100MHz memory bus speed. One
practical advantage of the 100MHz memory bus is that all processor speeds, starting with
350MHz, will be increments of 50. CPU speeds such as 233, 266, 333, etc. will be gone
forever. Now we can have easy to remember numbers such as 350, 400, 450, etc. The
increase from 66MHz to 100MHz memory bus will definitely help overall system performance
as CPU speeds are increasing by 50MHz almost every four or five months now. There's a
limitation in CPU speed in which the memory bus becomes the bottleneck. Running the memory
bus at 100MHz requires a new type of SDRAM DIMM called PC100; typically, PC100 SDRAMs are
rated at 8ns or faster.
The BX also have a new feature called Open Page Architecture (OPA). This allows the
Pentium II processor to leave "tabs" on virtual memory page addresses. So
instead of wasting valuable CPU cycles looking for a specific memory page, OPA will allow
the CPU to index the page immediately. Intel claims this will net a 3-5% performance
improvement for graphics intensive applications.
Initially, the BX will be paired with the Intel PIIX4-E I/O controller. (The PIIX4-E
controller governs the system memory and I/O such as the two USB ports and the
UltraDMA/33
IDE ports.) Later on, this will be changed to the PIIX6 controller, which will add support
for Firewire or IEEE 1394 and four USB ports. |
Intel 440BX AGPset Block
Diagram
Beginning with the Pentium class 430TX
PCIset, Intel divided their future
chipsets into two major components: Northbridge and Southbridge. Essentially, the
Nothbridge interface with the processor, memory subsystem, cache, AGP, and PCI slots. The
task of controlling the I/O and legacy ISA slots is left to the Southbridge. This enables
Intel to replace the Southbridge with new controllers (such as the upcoming PIIX6 with
Firewire support) without redesigning the entire chipset. And it will allow motherboard
designers to choose which Southbridge they wish to use for cost purposes.
Note that the AGP slot is now running at a full 133MHz with the BX AGPset. This is up
from 66MHz on the previous LX AGPset.
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